Digital shift control for vehicular transmission

ABSTRACT

To change the speed ratio of an automatically shiftable power train by which the torque of an engine is transmitted to the traction wheels of a vehicle, a logic circuit emits commands to respective solenoid valves in response to a combination of operating parameters such as vehicle speed, engine temperature, accelerator position and road gradient. Speed is measured by a pulse generator, coupled with the output shaft of the transmission, whose pulses are counted by an accumulator that is periodically reset by a timing circuit and whose count between resettings is fed to the logic circuit together with signals indicating the position of a manual speed selector. The remaining parameters are used to modify the rhythm of the timer or the operation of a decoder inserted between the accumulator and the logic circuit.

0 United States Patent 1191 [111 3,732,755 Beig et a1. ay 15, 1973 s41DIGITAL SHIFT CONTROL FOR 3,448,640 6/1969 Nelson ..74/7s2 A VEHICULARTRANSMISSION 3,572,168 3/1971 ..74/752 A 3,572,176 3/1971 ..74/866 1InventOfSI Willl Belg, Waggershausen; Willi 3,604,288 9 1971 Mori..74/866 Kuhnle, Friedrichshagen; Herbert Seibold, Mariabrunn, all ofGerprimary E i c Husar v y A ttorney- Karl F. Ross [73] Assignee:Zahnradfabrik Friedrichshaten Aktiengesellschaft, Fried richshafen, [57] ABSTRACT Germany To change the speed ratio of an automaticallyshifta- [22] Filed: Man 18 1971 ble power train by which the torque ofan engine is transmitted to the traction wheels of a vehicle, a logic 1PP 125,633 circuit emits commands to respective solenoid valves inresponse to a combination of operating parameters [30] ForeignApplication Prior), Data such as vehicle speed, engine temperature,accelerator pos1t1on and road gradlent. Speed 1s measured by a Mar. 19,1970 Germany ..P 20 13 079.4 pulse generator coupled with the outputshaft of the transmission, whose pulses are counted by an accumul latorthat is periodically reset by a timing circuit and 74/752 whose countbetween resettings is fed to the logic cir- [51] Iltl. Cl. .360]; 21/00Quit together with signals indicating the position of a [58] Field OfSearch ..74/866, 365, 336, manual s eed selector, The remainingparameters are 74/752 752 D used to modify the rhythm of the timer orthe operation of a decoder inserted between the accumulator [56]References Cited and the logic circuit.

UNITED STATES PATENTS 7 Claims, 8 Drawing Figures 3,628,642 12/1971Rauenel ..74/866 RP R N o o 20A 20 l COUNTER DECODER 1 1 LOAD I9 TEMI?GRADIENT 57 a jg-5 I BANK/"G CLOCK sm GE s'/ Fr 7a. lllllllHHHHHIIHIII'IHIHlmll lmllllllllllllllIIHIHIIHIIHHHPATENTEUHAY151975 LHP U 'l U U U SHEET 0F 5 GI U\CP' cP LI FIG. 7

-JLJ DIGITAL SHIFT CONTROL FOR VEIIICULAR TRANSMISSION Our presentinvention relates to an automatic gearshifting system, i.e. a system forchanging the speed ratio of a power train in a transmission of anautomotive vehicle in response to changes of one or more operatingparameters such as vehicle speed, transmission or engine temperature,engine load (as detemined by the position of the vehicular acceleratoror throttle) and the nature of the terrain.

Systems are known which evaluate combinations of several such parameterswith the aid of hydraulic valves to operate associated gear-shiftcontrols, generally in the form of hydraulic clutches and/or brakes forselectively entraining or arresting different elements of aplanetary-gear coupling inserted between the engine and a driven shaftconnected with the traction wheels of the vehicle. Reference may be madein this connection to commonly owned application Ser. No. 817,984 filedApr. 21, 1969 by Hansjorg Dach, now US. Pat. No. 3,580,112.

If a larger number of parameters are to be taken into consideration,such hydraulic processors tend to become rather complicated. The objectof our present invention, therefore, is to provide a shift-controlsystem for the purpose set forth wherein the switchover points, i.e. thespeed levels at which the system shifts to a higher or lower gear, canbe conveniently altered in response to a variety of conditions.

This object is realized, pusuant to our present invention, by theprovision of an electric pulse generator which is coupled to the drivenshaft of the transmission to measure the vehicular speed by producing atrain of rate pulses of a cadence proportional to that speed. Anaccumulator stage counts the number of rate pulses occurring within acertain period determined by an associated timing stage. The count ofthese rate pulses is fed to an actuating circuit which operates theconventional gear-shifting mechanism in response thereto, thus upon theattainment of a certain speed level by the accelerating or deceleratingvehicle.

The processor which controls the gear-shift actuators, and whichincludes the aforementioned accumulator and timing stages, alsocomprises circuitry for modifying the response of the actuators to thecount of the .rate pulses under the control of ancillary information fedinto it together with the rate pulses from the transmission-drivengenerator. This ancillary information, based upon one or more of theaforementioned parameters, may be utilized by the processor in severalways including a variation of the duration of a counting periodestablished by the timing stage and/or an alteration of the mode ofoperation of a decoder which translates the count of the accumulatorstage into a command for the gear-shift actuators.

For the purpose of varying the counting interval in response to one ormore operating parameters other than vehicle speed, the timing stage mayinclude a clock working into an adjustable frequency divider whosedivision ratio is controlled by the corresponding parameter sensor orsensors.

If the length of a counting period is variable, the timing stage mayinclude a second clock measuring a series of invariable gating intervalswhich are substantially longer than the framing cycles determining thecounting periods, with registration of the number of framing cycles pergating interval in a second accumulator stage; the count of theseframing cycles per gating interval may then be used, according toanother feature of our invention, as a corrective variable which jointlywith the count of the rate pulses controls the operation of thegear-shift actuators.

With such a system the ancillary information arriving at the processor,partly in analog form, can be readily converted into binary signals tobe utilized in a logic network for the control of the power stage of thegearshifting mechanism.

The above and other features of our invention will be described indetail hereinafter with reference to the accompanying drawing in which:

FIG. 1 is a block diagram of a relatively simple automatic gear-shiftingsystem embodying our invention;

FIG. 2 is a set of graphs relating to the operation of the system ofFIG. 1;

FIGS. 3, 4, 5 and 6 are block diagrams similar to FIG. 1 butrepresenting four more sophisticated embodiments;

FIG. 7 is a set of graphs relating to the system of FIG. 3; and

FIG. 8 is a more detailed circuit diagram of a system embodying featuresfrom preceding embodiments.

The system of FIG. 1 is designed for the control of an automatictransmission in an otherwise conventional automotive vehicle, notfurther illustrated, which includes a driver-operated selector 20 whoselever 20a in this simplified case has only three positions, namely N(neutral), D (drive) and R (reverse). For purposes of the presentinvention, only the forward position D is of interest; in neutral andreverse, the selector deenergizes the other elements shown in FIG. 1.

The vehicular transmission, generally designated 29, has an output shaft7 which forms part of a pulse generator 30 with an output lead 99terminating at the stepping input of a digital counter 22 in anaccumulator stage of a processor generally designated 100. The processoris connected to selector 20 via a lead 98 and also receives, fromexternal sources not shown in FIG. 1 but illustrated in FIG. 8 anddescribed hereinafter, a combination of ancillary signals on severalinput leads 49, 50, 51 and 52. It may be assumed, for example, that lead49 is energized by an analog voltage proportional to engine load, lead50 carries a signal corresponding to the temperature of the engineand/or the transmission, lead 51 supplies an analog voltage proportionalto the road gradient or slope (and of a polarity indicating ascending ordescending terrain), and lead 52 provides information on transverseinclination (banking) of the roadway. Leads 49 52 jointly control theoperating cycle of a clock 21 in a timing stage of the processor, theoutput of this clock resetting the counter 22 at the end of a periodwhose duration changes under the control of the various parameters justdescribed.

The pulse generator 30 of FIG. 1 comprises (as more clearly shown inFIGS. 3 6) an electromagnetic pickup coil 30a juxtaposed with a pinwheel30b of ferromagnetic material, each pin inducing a pulse in the outputlead 99 upon moving past the coil 30a.

Generator 30 thus produces a train of rate pulses RP whose cadencevaries with the speed of shaft 7; within a timing period or framingcycle established by clock 21, accumulator 22 counts a number of theserate pulses and delivers this count to a decoder 23 determiningtherefrom the instant when the transmission 29 is to be shifted. At suchinstant the decoder 23 trips a power stage 28 within the processor 100to operate or deactivate the corresponding drive-establishing elements(clutches or brakes) here represented, diagrammatically, by a unit 36for the l 2 shift and a unit 37 for the 2 3 shift. Each of these unitsis shown to comprise a hydraulic valve 36ab 37a controlled by a solenoid36b, 37b, respectively.

The operation of the system of FIG. 1 will now be described withreference to FIG. 2 where graph shows the train of rate pulses RPdelivered by the generator 30 of FIG. 1; graph 2b indicates a set ofclock pulses CP generated by clock 21 to define framing cycles FC,whereas graph 2c shows the speed ratio l/r of the transmission (with r 1for third gear). The pulses RP and CP are plotted in terms of voltage Uagainst time t while the transmission ratio I/r is plotted againstvehicular speed it (in terms of RPM of shaft 7).

In FIG. 2 the rate pulses RP follow one another in progressively closersuccession, indicating an acceleration of the vehicle. The framingcycles FC vary somewhat in duration, the intervening clock pulses CPserving to reset the counter 22. The first fully illustrated framingcycle, for length 1,, encompasses a relatively small number of ratepulses RP whose counts is insufficient to shift the transmission 29 fromfirst to second gear. A later framing cycle of length t embraces asufficient number of rate pulses RP to reach a count s which trips the l2 gear shifter 36 of FIG. 1 so that the transmission now operates insecond gear. Thereafter, a further framing cycle of duration measures apulse count s which trips the 2 3 gear shifter 37 to switch thetransmission into third gear.

If the engine load increases, the signal on lead 49 reduces the lengthof the framing cycles FC so that the upshifting to second or third gear(as well as the downshifting to first and second gear) occurs at higherspeeds n. A rise in temperature, as determined by the sensor connectedto lead 50, has the opposite effect and advances the upshifting toreduce the speed of the transmission input shaft. During uphill driving,a voltage of one polarity on lead 51 shrinks the framing cycles to delaYthe upshift; during downhill driving, the voltage of opposite polarityexpands the framing cycles to advance the upshift or retard thedownshift. If the roadway is banked, as when the vehicle drives througha curve, voltage on lead 52 again reduces the duration of the framingcycles to keep the vehicle speed down and to increase the availabletorque.

FIG. 3 shows a more elaborate system in which elements corresponding tothose of FIG. 1 have been designated by the same reference numerals andwhich includes a second clock 24, another counter 25 which receives theclock pulses C? of timing stage 21 and is periodically reset by clockpulses CP of timing stage 24, a second decoder 26 following the counter25, and a logic network 27 connected to the outputs of decoders 23 and26 in order to operate the power stage 28. Selcctor 20 is here shown tohave a further forward position, L (low), which prevents an upshift intothird gear and forces a downshift if the handle 20a is moved into thatposition while the transmission is in high." The output lead 98 of theselector has a branch 98' extending to clock 21 and another branch 98"terminating at logic circuit 27 to modify the functioning of the latterin a manner more fully described below with reference to FIG. 8.

The operation of the system of FIG. 3 will be better understood from thediagram of FIG. 7. Graph shows the rate pulses RP which, in the interestof simplicity, have been assumed to recur with constant frequencythroughout the length of time considered. Graph 7b illustrates theframing cycles FC which are separated by clock pulses CP and duringwhich the accumulator 22 generates a count s as shown in graph 70. Graph7d depicts the clock pulses CP emanating from timing stage 24, thesepulses defining gating intervals GI of constant length substantiallyexceeding that of framing cycles FC. As shown in graph 7e, accumulator25 counts the number of clock pulses CP and therefore of framing cyclesFC per gating interval GI, this number S being delivered to decoder 26to codetermine the operation of logic circuit 27 jointly with the counts from stage 22 supplied to decoder 23.

The system of FIG. 4 differs from that of FIG. 3 mainly by the provisionof a frequency divider 42 inserted between clock 21 and counter 22, withthe clock operating on a correspondingly increased frequency. Two moreinput leads 53 and 54 are shown working into clock circuit 21, lead 53carrying a signal to indicate driving through a curve whereas lead 54 isenergized upon the tripping of a so-called kick-down switch in a fullydepressed position of the accelerator pedal. As is well known, and ashas been described in the above-identified Dach US. Pat. No. 3,580,] 12,the kick-down switch serves to delay the upshifting from second to thirdgear and to transpose the downshift from third to second gear to ahigher speed range.

In the selector 20 of FIG. 4, the low position L of FIG. 3 has beenreplaced by two positions 2 and l which serve to eliminate third andsecond gear, respectively. An additional'position M, used for mountaindriving and in sports cars, extends the ranges of first and second gearby assigning higher speed levels to the corresponding switchover points.The second clock. 24, counter 25 and decoder 26, omitted in FIGS. 4 6,could also be included in these embodiments (cf. FIG.

The modification of FIG. 5 comprises the same elements as the embodimentof FIG. 4, yet with the inputs 49 54 and 98' transferred from clockcircuit 21 to the divider stage 42 to vary the cadence of the clockpulses CP.

In FIG. 6 these inputs have all been relocated to the input side ofdecoder 23 to control the evaluation of the count s rather than thecadence of the zero-setting pulses CP which in this case recur at aconstant frequency.

Reference will now be made to FIG. 8 for a detailed description ofrepresentative sensors for the various ancillary parameters discussedabove, and of the circuits controlled thereby.

In FIG. 8 the handle 20a of selector 20 has the same six positions as inFIG. 6; an accelerator pedal 21, depressible against a spring 102, tripsin its bottom position a kick-down switch 103 which normally energizes alead 54' and in its tripped state energizes a lead 54" (the two leadstogether are the equivalent of lead 54 in FIGS. 4 6). Accelerator 101also controls, via a linkage 104, a variable resistor 105 connectedbetween negative battery potential (ground) and lead 49. Temperature ismeasured by a thermistor 106 (here of the negative type) connectedbetween positive battery potential and lead 50. Resistor 105 andthermistor 106 form part of a voltage divider including furtherresistors 107, 108, 109, 110, 111, 112 in series thereiwth.

The road gradient is determined by a pendulum switch 113 vhich swings inthe direction of travel and, upon displacement from its normal positionagainst the force of a pair of centering springs, varies the inductivityof a respective coil 114 or 115 by altering its distance from a magneticpole piece 116 or 117 whereby an alternating current from a source 118is intensified or attenuated; a solenoid 119 in series with coil 114 ora solenoid 120 in series with coil 115 is thereby actuated to vary themagnitude of resistance 110 or 111, respectively. The pendulum switch113 could also be utilized to detect acceleration or deceleration.

The banking of the roadway is sensed by a U-tube 121 which is filledwith liquid and lies in a transverse plane of the vehicle; a float inone of the arms of the U supports a magnetic core 122 surrounded by acoil 123 which is energized from the a-c source 118 in series with asolenoid 124 to control the magnitude of resistance 109. With the core122 normally centered in coil 123, an inclination of the vehicle toeither side reduces the inductance of the coil and actuates the solenoid124 to diminish the resistance 109 to a corresponding extent.

Another pendulum switch 125 swings in a transverse plane of the vehicleand engages either of two associated contacts 126, 127 to short-circuitthe resistor 107 whenever the centrifugal force exerted thereon in acurve (and incompletely balanced by the banking of the roadway) exceedsthe restraining force of its centering springs. Resistor 107 is alsoshort-circuitable by the manual displacement ofa switch 128 which isoperated by the driver in the conventional manner to signal a turn tothe left or to the right.

Leads 51 and 51", shown in FIG. 8 as extending from pendulum switch 113,are represented by the single lead 51 in FIGS. 1 and 3 6. The outputleads of float-switch 121 and pendulum switch 125 have been respectivelydesignated 52 and 53, in conformity with the proceding Figures.

A tap on the voltage divider 105 112, specifically the junction J of itssections 110 and 111, is connected to the frequency divider 42 hereshown as comprising a capacitor 129 connected via a charging resistor130 to the output of clock 21 which delivers a train of timing pulses TPthereto. Capacitor 129 is connected to the aforementloned tap through aZener diode 131 in series with a resistor 132, their junction being tiedto the switching input of a monoflop 133 having its offnormal outputconnected to the resetting input of counter 22 and the stepping input ofcounter 25. The clock pulses CP appear on this monoflop output to startsuccessive framing cycles FC (FIGS. 2 and 7) as described above.

The decoder 23 has been shown in FIG. 8 as including a set of flip-flops134, 135, 136, 137 and 138 connected to respective stage outputs ofcounter 22, these stage outputs bearing (in ascending order) thedesignations n,', m, n n," and n which denote different speed levels asestablished by the count of rate pulses RP within a framing cycle FC.Since the length of such a framing cycle is variable under the controlof the severalparameters discussed above, in a manner more fullydescribed hereinafter, only the relative values of these speed levelsare significant. More particularly, speed level r determines the upshiftfrom first to see- 0nd gear whereas speed level n establishes theupshift from second to third gear; speed level n marks the downshiftfrom third to second gear, while speed level n, commands the downshiftfrom second to first gear. Speed level n, designates the point where theswitchover from third to second gear occurs under kickdown conditions,the span n n," being considerably smaller than the span n m The relativeoffset between corresponding upshifting and downshifting points isdesigned to stabilize the system against excessive fluctuations, aspointed out in the above-identified Dach U.S. Pat. No. 3,580,112 patent.

The logic circuit 27 comprises a pair of further flipflops 139, 140, thetwo networks 23 and 27 being interconnected by way of several AND gates141-146 and OR gates 147-149 which could be considered included ineither network and have been partly illustrated as components of decoder23. A further AND gate 150, connected to the set output of flip-flop 139and to the reset output of flip-flop 140, feeds an amplifier 152 inpower stage 28 to bring about the establishment of the second geardriving mode; two further amplifiers 151 and 153 in that power stage aredirectly energized by the reset output of flip-flop 139 and the setoutput of flip-flop 140, respectively, for establishing the first gearand third gear" modes. The portion of the power stage includingamplifiers 151-153 receives current from the vehicular battery, via anOR gate 154, whenever selector lever 20a is in one of its four forwardpositions D, M, 2 or 1. in neutral (N) the power stage is de-activated,whereas in reverse (R) another amplifier 155 is energized to make thedriven shaft 7 rotate in the opposite direction.

Flip-flop 139 las its setting input connected to the output of AND gate146 and has its resetting input connected to the output of AND gate 141by way of OR gate 147 which is also energized from selector 20 in the 1position of its handle so that flip-flop 139 cannot be set in thatselector position and amplifier 151 remains active to the exclusion ofamplifier 152. Flip-flop 140 has its setting input tied to the output ofAND gate 145 and has its resetting input tied to the output of AND gate146 through OR gate 149 which also receives operating voltage, via an ORgate 156, in positions 1 and 2 of the selector so that the flip-flop 140cannot be set under these circumstances and amplifier 153 is alsoinoperative.

1n selector positon M the handle 20a energizes a lead 157 to actuate arelay 158 which thereupon shortcircuits the resistor 108 in the voltagedivider -112.

AND gate 146 has one input connected to the set output of flip-flop andhas another input energizable from AND gate 142 or AND gate 143 via ORgate 148. AND gates 142 and 143 have inputs respectively connected toleads 54' and 54",AND gate 142 responding to a resetting of flip-flop136 whereas AND gate 143 similarly responds to the resetting offlip-flop 137. AND gate 141 responds to the resetting of flipflop 134.And gate has an input directly connected to the output of AND gate 150.The reset output of flipflop 139 is connected to one of the inputs ofAND gate 144. Each AND gate 141-145 also has one input connected to alead 159 extending from the output of clock 24. AND gates 144 and 145each have an input connected to the set output of flip-flops 135 and138, respectively.

Decoder 26 includes a flip-flop 161 which is settable by pulses s via alead 160 upon energization of a stage of counter 25 and is periodicallyreset, together with that counter, by the pulses C? from clock 24. Theset output of flip-flop 161 is fed to further inputs of AND gates 144and 145 which are thus inhibited if the flipflop 161 is not set during agating inverval GI (graph 7d), i.e. if the number of framing cycles FC(graph 7b) per gating interval is unduly reduced by a coincidence ofconditions (e.g. small load, high temperature) which could result inpremature upshifting.

The flip-flops 134-138 have their resetting inputs connected through adelay network 162 to lead 159 so as to be jointly reset shortly afterthe end of any gating interval GI. Monoflop 133 is tripped when thecharge of condenser 129, i.e. the sum of timing pulses TP fed into itfrom clock 21, exceeds the breakdown potential of Zener diode 131 whichis biased by voltage divider 105-112 through resistor 132. Thus, themagnitude of th biasing potential determines the frequency at which themonoflop is reversed to emit a clock pulse C? at the start of a newframing cycle. This frequency, therefore, rises if the junction J of thevoltage divider is driven more negative and drops if it is driven morepositive. If the load increases and accelerator pedal 101 is depressed,linkage 104 reduces the resistance 49 to let the monoflop 133 fire morefrequently; this means a contraction of framing cycles FC so that allthe switchover points n,, n, etc. are effectively raised in terms ofactual vehicular speed inasmuch as rate pulses RP must follow oneanother more quickly to reach a given count within a shortened cycle. Tothe same effect is a shortcircuiting of resistor 107 upon turning, ashorting of resistor 108 by relay 158 in selector position M, adiminution of resistance 109 during banking, and a reduction ofresistance 110 on uphill driving. Conversely, a' reduction of resistance111 on downhill driving or of resistance 106 in response to highertransmission or engine temperatures increases the bias of Zener diode131 and lengthens the charging period of capacitor 129, therebyextending the framing cycles FC and transporting the switchover pointsto lower vehicular speeds. With all the flip-flops 134-138 reset, ANDgate 141 conducts whenever lead 159 is energized at the end of a framingcycle. This operation has no further effect since flip-flop 139 will bereset at such time. Amplifier 151 is operated to establish the highesttorque ratio r corresponding to first gear.

As the count reaches the stage n,', flip-flop 134 is set to block theAND gate 141 without any immediate effect. Upon further acceleration,stage n, is reached so that flip-flop 135 is set. I

As long as counter 25 has not been loaded sufficiently to trip theflip-flop 161, AND gate 144 is blocked so that the setting of flip-flop135 is ineffectual. With normal operation, however, flip-flop 161 willbe reversed at some point in the ensuing gating interval so that, beforethe occurrence of the next pulse CP' at the end of that interval, allthe inputs of AND gate 144 are energized whereby flip-flop 139 istripped to initiate the 1-2 upshift, i.e. to activate the amplifier 152.

Upon further acceleration, the count reaches stage n, with consequentsetting of flip-flop 136 which is 6 without significance at this time.The same applies to the subsequent setting of flip-flop 137 from theoutput of stage n Finally, stage output n is energized to switch theflipflop 138 whereby, with AND gate 150 conductive at this time, ANDgate 145 sets the flip-flop 140 in the presence of the next clock pulseC? if the decoder 26 permits this operation. The system is now operatingin third gear.

Upon subsequent deceleration, and with kick-down switch 103 in itsillustrated normal position, flip-flop 140 cannot be reset as long asAND gate 142 is blocked by the prior setting of flip-flop 136 during thesame gating interval, i.e. while the speed equals or exceeds the level nWhen the speed drops below that level, AND gate 142 responds to the nextpulse CP' and, via gates 148, 146 and 149, resets the flip-flop 140 fora downshift to second gear.

Ifa further slowdown takes the speed below level n,', flip-flop 134remains reset throughout the following gating interval GI so that thenext clock pulse C? resets the flip-flop 139 by way of gates 141 and147. The transmission has now returned to first gear.

In the foregoing description it has been assumed that selector lever 20ais in its illustrated position D or, possibly, in the adjacent positionM. If, from either of these positions, it is moved to position 2" or 1,"flip-flop 140 in the former case and both flio-flops 139 and 140 in thelatter case would be promptly reset (if previously set) so that thesystem would return to the corresponding lower transmission ratio.

lf, with flip-flops 139 and 140 set to establish the third gear drivingmode, the operator depresses the pedal 101 sufficiently to reverse thekick-down switch 103, AND gate 142 is blocked whereas AND gate 143 isenabled to respond to a resetting of flip-flop 137 at speeds below leveln to reset the flip-flop 140 for the 2-3 downshift which thereforeoccurs at a higher speed level.

It will thus be apparent that the operation of the control system inresponse to the rate pulses RP can be modified (a) by directly orindirectly altering the cadence of clock pulses CP, as generally shownin FIGS. 1 and 3 5 and as illustrated more specifically in FIG. 8 forthe sensors associated with voltage divider 112, and/or (b) byintervening directly in the logic of the decoder, as broadly shown inFIG. 6 and as specifically illustrated in FIG. 8 for the kick-downcircuit 54, 54".

The various switches shown in FIG. 8, though illustrated as relativelymovable contacts, may be of the contactless type and may be combinedwith other circuit elements in an integrated solid-state or hybrid-typemodule. Analog values, such as those supplied by sensors 106, 113 and121, could also be digitized.

We claim:

1. In an automotive vehicle having an engine, a driven shaft, atransmission of variable speed ratio coupling said engine to said drivenshaft, fuel-control means for said engine and shift means for varyingsaid speed ratio, the combination therewith of:

electric pulse-generating means coupled with said driven shaft foremitting a train of rate pulses at a cadence proportional to the speedof said shaft; sensing means responsive to an operating parameteraffecting the optimum operating point of said shift means;

signal-generating means controlled by said sensing means to produce anoutput related to said operating parameter;

a processor having an input stage connected to said signal-generatingmeans; accumulator means in said processor coupled to saidpulse-generating means for counting said rate pulses;

timing means in said processor connected to said accumulator means forresetting same at the end of a recurrent counting period;

actuating means for said shift means controlled by said processor inresponse to a predetermined count of said rate pulses indicative ofshaft speed; and

modifying circuitry in said timing means responsive to said output foraltering the duration of said counting period, thereby varying the shaftspeed corresponding to said predetermined count.

2. The combination defined in claim 1 wherein said timing meanscomprises a first clock controlled by said modifying circuitry forgenerating a succession of framing cycles of variable length, definingsaid counting period, and a second clock measuring a series ofinvariable gating intervals substantially longer than said framingcycles, said processor including a second accumulator for registeringthe number of framing cycles per gating interval, said actuating meansbeing jointly controlled by said accumulators to operate said shiftmeans at an instant codetermined by said count and said number.

3. The combination defined in claim 2 wherein said timing meanscomprises a source of clock pulses and frequency-dividing meansconnected to said source for deriving from said clock pulses asuccession of lowercadence framing pulses of a length defining saidcounting period.

4. The combination defined in claim 4 wherein said modifying circuitryis connected to said frequencydividing means for varying the step-downratio thereof,

5. The combination defined in claim 1, further comprising a manualspeed-ratio selector with a plurality of operating positions and circuitmeans extending from said selector to said processor for blocking theresponse of said actuating means to said count in certain of saidoperating positions.

6. The combination defined in claim 1 wherein said pulse-generatingmeans comprises a ferromagnetic pinwheel on said driven shaft andinductive pickup means adjacent said pinwheel.

1. In an automotive vehicle having an engine, a driven shaft, atransmission of variable speed ratio coupling said engine to said drivenshaft, fuel-control means for said engine and shift means for varyingsaid speed ratio, the combination therewith of: electricpulse-generating means coupled with said driven shaft for emitting atrain of rate pulses at a cadence proportional to the speed of saidshaft; sensing means responsive to an operating parameter affecting theoptimum operating point of said shift means; signal-generating meanscontrolled by said sensing means to produce an output related to saidoperating parameter; a processor having an input stage connected to saidsignalgenerating means; accumulator means in said processor coupled tosaid pulsegenerating means for counting said rate pulses; timing meansin said processor connected to said accumulator means for resetting sameat the end of a recurrent counting period; actuating means for saidshift means controlled by said processor in response to a predeterminedcount of said rate pulses indicative of shaft speed; and modifyingcircuitry in said timing means responsive to said output for alteringthe duration of said counting period, thereby varying the shaft speedcorresponding to said predetermined count.
 2. The combination defined inclaim 1 wherein said timing means comprises a first clock controlled bysaid modifying circuitry for generating a succession of framing cyclesof variable length, defining said counting period, and a second clockmeasuring a series of invariable gating intervals substantially longerthan said framing cycles, said processor including a second accumulatorfor registering the number of framing cycles per gating interval, saidactuating means being jointly controlled by said accumulators to operatesaid shift means at an instant codetermined by said count and saidnumber.
 3. The combination defined in claim 2 wherein said timing meanscomprises a source of clock pulses and frequency-dividing meansconnected to said source for deriving from said clock pulses asuccession of lower-cadence framing pulses of a length defining saidcounting period.
 4. The combination defined in claim 4 wherein saidmodifying circuitry is connected to said frequency-dividing means forvarying the step-down ratio thereof.
 5. The combination defined in claim1, further comprising a manual speed-ratio selector with a plurality ofoperating positioNs and circuit means extending from said selector tosaid processor for blocking the response of said actuating means to saidcount in certain of said operating positions.
 6. The combination definedin claim 1 wherein said pulse-generating means comprises a ferromagneticpinwheel on said driven shaft and inductive pickup means adjacent saidpinwheel.
 7. The combination defined in claim 1 wherein said modifyingcircuitry comprises a logic network.